1use rustc_abi::CanonAbi;
2use rustc_middle::mir::BinOp;
3use rustc_middle::ty::Ty;
4use rustc_span::Symbol;
5use rustc_target::callconv::FnAbi;
6
7use crate::*;
8
9impl<'tcx> EvalContextExt<'tcx> for crate::MiriInterpCx<'tcx> {}
10pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
11 fn emulate_aarch64_intrinsic(
12 &mut self,
13 link_name: Symbol,
14 abi: &FnAbi<'tcx, Ty<'tcx>>,
15 args: &[OpTy<'tcx>],
16 dest: &MPlaceTy<'tcx>,
17 ) -> InterpResult<'tcx, EmulateItemResult> {
18 let this = self.eval_context_mut();
19 let unprefixed_name = link_name.as_str().strip_prefix("llvm.aarch64.").unwrap();
21 match unprefixed_name {
22 "isb" => {
23 let [arg] = this.check_shim(abi, CanonAbi::C, link_name, args)?;
24 let arg = this.read_scalar(arg)?.to_i32()?;
25 match arg {
26 15 => {
28 this.yield_active_thread();
29 }
30 _ => {
31 throw_unsup_format!("unsupported llvm.aarch64.isb argument {}", arg);
32 }
33 }
34 }
35
36 "neon.umaxp.v16i8" => {
41 let [left, right] = this.check_shim(abi, CanonAbi::C, link_name, args)?;
42
43 let (left, left_len) = this.project_to_simd(left)?;
44 let (right, right_len) = this.project_to_simd(right)?;
45 let (dest, lane_count) = this.project_to_simd(dest)?;
46 assert_eq!(left_len, right_len);
47 assert_eq!(lane_count, left_len);
48
49 for lane_idx in 0..lane_count {
50 let src = if lane_idx < (lane_count / 2) { &left } else { &right };
51 let src_idx = lane_idx.strict_rem(lane_count / 2);
52
53 let lhs_lane =
54 this.read_immediate(&this.project_index(src, src_idx.strict_mul(2))?)?;
55 let rhs_lane = this.read_immediate(
56 &this.project_index(src, src_idx.strict_mul(2).strict_add(1))?,
57 )?;
58
59 let res_lane = if this
61 .binary_op(BinOp::Gt, &lhs_lane, &rhs_lane)?
62 .to_scalar()
63 .to_bool()?
64 {
65 lhs_lane
66 } else {
67 rhs_lane
68 };
69
70 let dest = this.project_index(&dest, lane_idx)?;
71 this.write_immediate(*res_lane, &dest)?;
72 }
73 }
74
75 _ => return interp_ok(EmulateItemResult::NotSupported),
76 }
77 interp_ok(EmulateItemResult::NeedsReturn)
78 }
79}