rustc_hir_typeck/
inline_asm.rs

1use rustc_abi::FieldIdx;
2use rustc_ast::InlineAsmTemplatePiece;
3use rustc_data_structures::fx::FxIndexSet;
4use rustc_hir::def_id::DefId;
5use rustc_hir::{self as hir, LangItem};
6use rustc_middle::bug;
7use rustc_middle::ty::{self, Article, FloatTy, IntTy, Ty, TyCtxt, TypeVisitableExt, UintTy};
8use rustc_session::lint;
9use rustc_span::def_id::LocalDefId;
10use rustc_span::{Span, Symbol, sym};
11use rustc_target::asm::{
12    InlineAsmReg, InlineAsmRegClass, InlineAsmRegOrRegClass, InlineAsmType, ModifierInfo,
13};
14use rustc_trait_selection::infer::InferCtxtExt;
15
16use crate::FnCtxt;
17use crate::errors::RegisterTypeUnstable;
18
19pub(crate) struct InlineAsmCtxt<'a, 'tcx> {
20    target_features: &'tcx FxIndexSet<Symbol>,
21    fcx: &'a FnCtxt<'a, 'tcx>,
22}
23
24enum NonAsmTypeReason<'tcx> {
25    UnevaluatedSIMDArrayLength(DefId, ty::Const<'tcx>),
26    Invalid(Ty<'tcx>),
27    InvalidElement(DefId, Ty<'tcx>),
28    NotSizedPtr(Ty<'tcx>),
29    EmptySIMDArray(Ty<'tcx>),
30}
31
32impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
33    pub(crate) fn new(fcx: &'a FnCtxt<'a, 'tcx>, def_id: LocalDefId) -> Self {
34        InlineAsmCtxt { target_features: fcx.tcx.asm_target_features(def_id), fcx }
35    }
36
37    fn tcx(&self) -> TyCtxt<'tcx> {
38        self.fcx.tcx
39    }
40
41    fn expr_ty(&self, expr: &hir::Expr<'tcx>) -> Ty<'tcx> {
42        let ty = self.fcx.typeck_results.borrow().expr_ty_adjusted(expr);
43        let ty = self.fcx.try_structurally_resolve_type(expr.span, ty);
44        if ty.has_non_region_infer() {
45            Ty::new_misc_error(self.tcx())
46        } else {
47            self.tcx().erase_regions(ty)
48        }
49    }
50
51    // FIXME(compiler-errors): This could use `<$ty as Pointee>::Metadata == ()`
52    fn is_thin_ptr_ty(&self, span: Span, ty: Ty<'tcx>) -> bool {
53        // Type still may have region variables, but `Sized` does not depend
54        // on those, so just erase them before querying.
55        if self.fcx.type_is_sized_modulo_regions(self.fcx.param_env, ty) {
56            return true;
57        }
58        if let ty::Foreign(..) = self.fcx.try_structurally_resolve_type(span, ty).kind() {
59            return true;
60        }
61        false
62    }
63
64    fn get_asm_ty(
65        &self,
66        span: Span,
67        ty: Ty<'tcx>,
68    ) -> Result<InlineAsmType, NonAsmTypeReason<'tcx>> {
69        let asm_ty_isize = match self.tcx().sess.target.pointer_width {
70            16 => InlineAsmType::I16,
71            32 => InlineAsmType::I32,
72            64 => InlineAsmType::I64,
73            width => bug!("unsupported pointer width: {width}"),
74        };
75
76        match *ty.kind() {
77            ty::Int(IntTy::I8) | ty::Uint(UintTy::U8) => Ok(InlineAsmType::I8),
78            ty::Int(IntTy::I16) | ty::Uint(UintTy::U16) => Ok(InlineAsmType::I16),
79            ty::Int(IntTy::I32) | ty::Uint(UintTy::U32) => Ok(InlineAsmType::I32),
80            ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => Ok(InlineAsmType::I64),
81            ty::Int(IntTy::I128) | ty::Uint(UintTy::U128) => Ok(InlineAsmType::I128),
82            ty::Int(IntTy::Isize) | ty::Uint(UintTy::Usize) => Ok(asm_ty_isize),
83            ty::Float(FloatTy::F16) => Ok(InlineAsmType::F16),
84            ty::Float(FloatTy::F32) => Ok(InlineAsmType::F32),
85            ty::Float(FloatTy::F64) => Ok(InlineAsmType::F64),
86            ty::Float(FloatTy::F128) => Ok(InlineAsmType::F128),
87            ty::FnPtr(..) => Ok(asm_ty_isize),
88            ty::RawPtr(elem_ty, _) => {
89                if self.is_thin_ptr_ty(span, elem_ty) {
90                    Ok(asm_ty_isize)
91                } else {
92                    Err(NonAsmTypeReason::NotSizedPtr(ty))
93                }
94            }
95            ty::Adt(adt, args) if adt.repr().simd() => {
96                let fields = &adt.non_enum_variant().fields;
97                if fields.is_empty() {
98                    return Err(NonAsmTypeReason::EmptySIMDArray(ty));
99                }
100                let field = &fields[FieldIdx::ZERO];
101                let elem_ty = field.ty(self.tcx(), args);
102
103                let (size, ty) = match *elem_ty.kind() {
104                    ty::Array(ty, len) => {
105                        // FIXME: `try_structurally_resolve_const` doesn't eval consts
106                        // in the old solver.
107                        let len = if self.fcx.next_trait_solver() {
108                            self.fcx.try_structurally_resolve_const(span, len)
109                        } else {
110                            self.fcx.tcx.normalize_erasing_regions(
111                                self.fcx.typing_env(self.fcx.param_env),
112                                len,
113                            )
114                        };
115                        if let Some(len) = len.try_to_target_usize(self.tcx()) {
116                            (len, ty)
117                        } else {
118                            return Err(NonAsmTypeReason::UnevaluatedSIMDArrayLength(
119                                field.did, len,
120                            ));
121                        }
122                    }
123                    _ => (fields.len() as u64, elem_ty),
124                };
125
126                match ty.kind() {
127                    ty::Int(IntTy::I8) | ty::Uint(UintTy::U8) => Ok(InlineAsmType::VecI8(size)),
128                    ty::Int(IntTy::I16) | ty::Uint(UintTy::U16) => Ok(InlineAsmType::VecI16(size)),
129                    ty::Int(IntTy::I32) | ty::Uint(UintTy::U32) => Ok(InlineAsmType::VecI32(size)),
130                    ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => Ok(InlineAsmType::VecI64(size)),
131                    ty::Int(IntTy::I128) | ty::Uint(UintTy::U128) => {
132                        Ok(InlineAsmType::VecI128(size))
133                    }
134                    ty::Int(IntTy::Isize) | ty::Uint(UintTy::Usize) => {
135                        Ok(match self.tcx().sess.target.pointer_width {
136                            16 => InlineAsmType::VecI16(size),
137                            32 => InlineAsmType::VecI32(size),
138                            64 => InlineAsmType::VecI64(size),
139                            width => bug!("unsupported pointer width: {width}"),
140                        })
141                    }
142                    ty::Float(FloatTy::F16) => Ok(InlineAsmType::VecF16(size)),
143                    ty::Float(FloatTy::F32) => Ok(InlineAsmType::VecF32(size)),
144                    ty::Float(FloatTy::F64) => Ok(InlineAsmType::VecF64(size)),
145                    ty::Float(FloatTy::F128) => Ok(InlineAsmType::VecF128(size)),
146                    _ => Err(NonAsmTypeReason::InvalidElement(field.did, ty)),
147                }
148            }
149            ty::Infer(_) => bug!("unexpected infer ty in asm operand"),
150            _ => Err(NonAsmTypeReason::Invalid(ty)),
151        }
152    }
153
154    fn check_asm_operand_type(
155        &self,
156        idx: usize,
157        reg: InlineAsmRegOrRegClass,
158        expr: &'tcx hir::Expr<'tcx>,
159        template: &[InlineAsmTemplatePiece],
160        is_input: bool,
161        tied_input: Option<(&'tcx hir::Expr<'tcx>, Option<InlineAsmType>)>,
162    ) -> Option<InlineAsmType> {
163        let ty = self.expr_ty(expr);
164        if ty.has_non_region_infer() {
165            bug!("inference variable in asm operand ty: {:?} {:?}", expr, ty);
166        }
167
168        let asm_ty = match *ty.kind() {
169            // `!` is allowed for input but not for output (issue #87802)
170            ty::Never if is_input => return None,
171            _ if ty.references_error() => return None,
172            ty::Adt(adt, args) if self.tcx().is_lang_item(adt.did(), LangItem::MaybeUninit) => {
173                let fields = &adt.non_enum_variant().fields;
174                let ty = fields[FieldIdx::from_u32(1)].ty(self.tcx(), args);
175                // FIXME: Are we just trying to map to the `T` in `MaybeUninit<T>`?
176                // If so, just get it from the args.
177                let ty::Adt(ty, args) = ty.kind() else {
178                    unreachable!("expected first field of `MaybeUninit` to be an ADT")
179                };
180                assert!(
181                    ty.is_manually_drop(),
182                    "expected first field of `MaybeUninit` to be `ManuallyDrop`"
183                );
184                let fields = &ty.non_enum_variant().fields;
185                let ty = fields[FieldIdx::ZERO].ty(self.tcx(), args);
186                self.get_asm_ty(expr.span, ty)
187            }
188            _ => self.get_asm_ty(expr.span, ty),
189        };
190        let asm_ty = match asm_ty {
191            Ok(asm_ty) => asm_ty,
192            Err(reason) => {
193                match reason {
194                    NonAsmTypeReason::UnevaluatedSIMDArrayLength(did, len) => {
195                        let msg = format!("cannot evaluate SIMD vector length `{len}`");
196                        self.fcx
197                            .dcx()
198                            .struct_span_err(self.tcx().def_span(did), msg)
199                            .with_span_note(
200                                expr.span,
201                                "SIMD vector length needs to be known statically for use in `asm!`",
202                            )
203                            .emit();
204                    }
205                    NonAsmTypeReason::Invalid(ty) => {
206                        let msg = format!("cannot use value of type `{ty}` for inline assembly");
207                        self.fcx.dcx().struct_span_err(expr.span, msg).with_note(
208                            "only integers, floats, SIMD vectors, pointers and function pointers \
209                            can be used as arguments for inline assembly",
210                        ).emit();
211                    }
212                    NonAsmTypeReason::NotSizedPtr(ty) => {
213                        let msg = format!(
214                            "cannot use value of unsized pointer type `{ty}` for inline assembly"
215                        );
216                        self.fcx
217                            .dcx()
218                            .struct_span_err(expr.span, msg)
219                            .with_note("only sized pointers can be used in inline assembly")
220                            .emit();
221                    }
222                    NonAsmTypeReason::InvalidElement(did, ty) => {
223                        let msg = format!(
224                            "cannot use SIMD vector with element type `{ty}` for inline assembly"
225                        );
226                        self.fcx.dcx()
227                        .struct_span_err(self.tcx().def_span(did), msg).with_span_note(
228                            expr.span,
229                            "only integers, floats, SIMD vectors, pointers and function pointers \
230                            can be used as arguments for inline assembly",
231                        ).emit();
232                    }
233                    NonAsmTypeReason::EmptySIMDArray(ty) => {
234                        let msg = format!("use of empty SIMD vector `{ty}`");
235                        self.fcx.dcx().struct_span_err(expr.span, msg).emit();
236                    }
237                }
238                return None;
239            }
240        };
241
242        // Check that the type implements Copy. The only case where this can
243        // possibly fail is for SIMD types which don't #[derive(Copy)].
244        if !self.fcx.type_is_copy_modulo_regions(self.fcx.param_env, ty) {
245            let msg = "arguments for inline assembly must be copyable";
246            self.fcx
247                .dcx()
248                .struct_span_err(expr.span, msg)
249                .with_note(format!("`{ty}` does not implement the Copy trait"))
250                .emit();
251        }
252
253        // Ideally we wouldn't need to do this, but LLVM's register allocator
254        // really doesn't like it when tied operands have different types.
255        //
256        // This is purely an LLVM limitation, but we have to live with it since
257        // there is no way to hide this with implicit conversions.
258        //
259        // For the purposes of this check we only look at the `InlineAsmType`,
260        // which means that pointers and integers are treated as identical (modulo
261        // size).
262        if let Some((in_expr, Some(in_asm_ty))) = tied_input {
263            if in_asm_ty != asm_ty {
264                let msg = "incompatible types for asm inout argument";
265                let in_expr_ty = self.expr_ty(in_expr);
266                self.fcx
267                    .dcx()
268                    .struct_span_err(vec![in_expr.span, expr.span], msg)
269                    .with_span_label(in_expr.span, format!("type `{in_expr_ty}`"))
270                    .with_span_label(expr.span, format!("type `{ty}`"))
271                    .with_note(
272                        "asm inout arguments must have the same type, \
273                        unless they are both pointers or integers of the same size",
274                    )
275                    .emit();
276            }
277
278            // All of the later checks have already been done on the input, so
279            // let's not emit errors and warnings twice.
280            return Some(asm_ty);
281        }
282
283        // Check the type against the list of types supported by the selected
284        // register class.
285        let asm_arch = self.tcx().sess.asm_arch.unwrap();
286        let allow_experimental_reg = self.tcx().features().asm_experimental_reg();
287        let reg_class = reg.reg_class();
288        let supported_tys = reg_class.supported_types(asm_arch, allow_experimental_reg);
289        let Some((_, feature)) = supported_tys.iter().find(|&&(t, _)| t == asm_ty) else {
290            let mut err = if !allow_experimental_reg
291                && reg_class.supported_types(asm_arch, true).iter().any(|&(t, _)| t == asm_ty)
292            {
293                self.tcx().sess.create_feature_err(
294                    RegisterTypeUnstable { span: expr.span, ty },
295                    sym::asm_experimental_reg,
296                )
297            } else {
298                let msg = format!("type `{ty}` cannot be used with this register class");
299                let mut err = self.fcx.dcx().struct_span_err(expr.span, msg);
300                let supported_tys: Vec<_> =
301                    supported_tys.iter().map(|(t, _)| t.to_string()).collect();
302                err.note(format!(
303                    "register class `{}` supports these types: {}",
304                    reg_class.name(),
305                    supported_tys.join(", "),
306                ));
307                err
308            };
309            if let Some(suggest) = reg_class.suggest_class(asm_arch, asm_ty) {
310                err.help(format!("consider using the `{}` register class instead", suggest.name()));
311            }
312            err.emit();
313            return Some(asm_ty);
314        };
315
316        // Check whether the selected type requires a target feature. Note that
317        // this is different from the feature check we did earlier. While the
318        // previous check checked that this register class is usable at all
319        // with the currently enabled features, some types may only be usable
320        // with a register class when a certain feature is enabled. We check
321        // this here since it depends on the results of typeck.
322        //
323        // Also note that this check isn't run when the operand type is never
324        // (!). In that case we still need the earlier check to verify that the
325        // register class is usable at all.
326        if let Some(feature) = feature {
327            if !self.target_features.contains(feature) {
328                let msg = format!("`{feature}` target feature is not enabled");
329                self.fcx
330                    .dcx()
331                    .struct_span_err(expr.span, msg)
332                    .with_note(format!(
333                        "this is required to use type `{}` with register class `{}`",
334                        ty,
335                        reg_class.name(),
336                    ))
337                    .emit();
338                return Some(asm_ty);
339            }
340        }
341
342        // Check whether a modifier is suggested for using this type.
343        if let Some(ModifierInfo {
344            modifier: suggested_modifier,
345            result: suggested_result,
346            size: suggested_size,
347        }) = reg_class.suggest_modifier(asm_arch, asm_ty)
348        {
349            // Search for any use of this operand without a modifier and emit
350            // the suggestion for them.
351            let mut spans = vec![];
352            for piece in template {
353                if let &InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span } = piece
354                {
355                    if operand_idx == idx && modifier.is_none() {
356                        spans.push(span);
357                    }
358                }
359            }
360            if !spans.is_empty() {
361                let ModifierInfo {
362                    modifier: default_modifier,
363                    result: default_result,
364                    size: default_size,
365                } = reg_class.default_modifier(asm_arch).unwrap();
366                self.tcx().node_span_lint(
367                    lint::builtin::ASM_SUB_REGISTER,
368                    expr.hir_id,
369                    spans,
370                    |lint| {
371                        lint.primary_message("formatting may not be suitable for sub-register argument");
372                        lint.span_label(expr.span, "for this argument");
373                        lint.help(format!(
374                            "use `{{{idx}:{suggested_modifier}}}` to have the register formatted as `{suggested_result}` (for {suggested_size}-bit values)",
375                        ));
376                        lint.help(format!(
377                            "or use `{{{idx}:{default_modifier}}}` to keep the default formatting of `{default_result}` (for {default_size}-bit values)",
378                        ));
379                    },
380                );
381            }
382        }
383
384        Some(asm_ty)
385    }
386
387    pub(crate) fn check_asm(&self, asm: &hir::InlineAsm<'tcx>) {
388        let Some(asm_arch) = self.tcx().sess.asm_arch else {
389            self.fcx.dcx().delayed_bug("target architecture does not support asm");
390            return;
391        };
392        let allow_experimental_reg = self.tcx().features().asm_experimental_reg();
393        for (idx, &(op, op_sp)) in asm.operands.iter().enumerate() {
394            // Validate register classes against currently enabled target
395            // features. We check that at least one type is available for
396            // the enabled features.
397            //
398            // We ignore target feature requirements for clobbers: if the
399            // feature is disabled then the compiler doesn't care what we
400            // do with the registers.
401            //
402            // Note that this is only possible for explicit register
403            // operands, which cannot be used in the asm string.
404            if let Some(reg) = op.reg() {
405                // Some explicit registers cannot be used depending on the
406                // target. Reject those here.
407                if let InlineAsmRegOrRegClass::Reg(reg) = reg {
408                    if let InlineAsmReg::Err = reg {
409                        // `validate` will panic on `Err`, as an error must
410                        // already have been reported.
411                        continue;
412                    }
413                    if let Err(msg) = reg.validate(
414                        asm_arch,
415                        self.tcx().sess.relocation_model(),
416                        self.target_features,
417                        &self.tcx().sess.target,
418                        op.is_clobber(),
419                    ) {
420                        let msg = format!("cannot use register `{}`: {}", reg.name(), msg);
421                        self.fcx.dcx().span_err(op_sp, msg);
422                        continue;
423                    }
424                }
425
426                if !op.is_clobber() {
427                    let mut missing_required_features = vec![];
428                    let reg_class = reg.reg_class();
429                    if let InlineAsmRegClass::Err = reg_class {
430                        continue;
431                    }
432                    for &(_, feature) in reg_class.supported_types(asm_arch, allow_experimental_reg)
433                    {
434                        match feature {
435                            Some(feature) => {
436                                if self.target_features.contains(&feature) {
437                                    missing_required_features.clear();
438                                    break;
439                                } else {
440                                    missing_required_features.push(feature);
441                                }
442                            }
443                            None => {
444                                missing_required_features.clear();
445                                break;
446                            }
447                        }
448                    }
449
450                    // We are sorting primitive strs here and can use unstable sort here
451                    missing_required_features.sort_unstable();
452                    missing_required_features.dedup();
453                    match &missing_required_features[..] {
454                        [] => {}
455                        [feature] => {
456                            let msg = format!(
457                                "register class `{}` requires the `{}` target feature",
458                                reg_class.name(),
459                                feature
460                            );
461                            self.fcx.dcx().span_err(op_sp, msg);
462                            // register isn't enabled, don't do more checks
463                            continue;
464                        }
465                        features => {
466                            let msg = format!(
467                                "register class `{}` requires at least one of the following target features: {}",
468                                reg_class.name(),
469                                features
470                                    .iter()
471                                    .map(|f| f.as_str())
472                                    .intersperse(", ")
473                                    .collect::<String>(),
474                            );
475                            self.fcx.dcx().span_err(op_sp, msg);
476                            // register isn't enabled, don't do more checks
477                            continue;
478                        }
479                    }
480                }
481            }
482
483            match op {
484                hir::InlineAsmOperand::In { reg, expr } => {
485                    self.check_asm_operand_type(idx, reg, expr, asm.template, true, None);
486                }
487                hir::InlineAsmOperand::Out { reg, late: _, expr } => {
488                    if let Some(expr) = expr {
489                        self.check_asm_operand_type(idx, reg, expr, asm.template, false, None);
490                    }
491                }
492                hir::InlineAsmOperand::InOut { reg, late: _, expr } => {
493                    self.check_asm_operand_type(idx, reg, expr, asm.template, false, None);
494                }
495                hir::InlineAsmOperand::SplitInOut { reg, late: _, in_expr, out_expr } => {
496                    let in_ty =
497                        self.check_asm_operand_type(idx, reg, in_expr, asm.template, true, None);
498                    if let Some(out_expr) = out_expr {
499                        self.check_asm_operand_type(
500                            idx,
501                            reg,
502                            out_expr,
503                            asm.template,
504                            false,
505                            Some((in_expr, in_ty)),
506                        );
507                    }
508                }
509                hir::InlineAsmOperand::Const { anon_const } => {
510                    let ty = self.expr_ty(self.tcx().hir_body(anon_const.body).value);
511                    match ty.kind() {
512                        ty::Error(_) => {}
513                        _ if ty.is_integral() => {}
514                        _ => {
515                            self.fcx
516                                .dcx()
517                                .struct_span_err(op_sp, "invalid type for `const` operand")
518                                .with_span_label(
519                                    self.tcx().def_span(anon_const.def_id),
520                                    format!("is {} `{}`", ty.kind().article(), ty),
521                                )
522                                .with_help("`const` operands must be of an integer type")
523                                .emit();
524                        }
525                    }
526                }
527                // Typeck has checked that SymFn refers to a function.
528                hir::InlineAsmOperand::SymFn { expr } => {
529                    let ty = self.expr_ty(expr);
530                    match ty.kind() {
531                        ty::FnDef(..) => {}
532                        ty::Error(_) => {}
533                        _ => {
534                            self.fcx
535                                .dcx()
536                                .struct_span_err(op_sp, "invalid `sym` operand")
537                                .with_span_label(
538                                    expr.span,
539                                    format!("is {} `{}`", ty.kind().article(), ty),
540                                )
541                                .with_help(
542                                    "`sym` operands must refer to either a function or a static",
543                                )
544                                .emit();
545                        }
546                    }
547                }
548                // AST lowering guarantees that SymStatic points to a static.
549                hir::InlineAsmOperand::SymStatic { .. } => {}
550                // No special checking is needed for labels.
551                hir::InlineAsmOperand::Label { .. } => {}
552            }
553        }
554    }
555}
rustc_hir_typeck/inline_asm.rs

rustc_hir_typeck/
inline_asm.rs
