rustc_target/callconv/
x86.rs

1use rustc_abi::{
2    AddressSpace, Align, BackendRepr, HasDataLayout, Primitive, Reg, RegKind, TyAbiInterface,
3    TyAndLayout,
4};
5
6use crate::callconv::{ArgAttribute, FnAbi, PassMode};
7use crate::spec::{HasTargetSpec, RustcAbi};
8
9#[derive(PartialEq)]
10pub(crate) enum Flavor {
11    General,
12    FastcallOrVectorcall,
13}
14
15pub(crate) struct X86Options {
16    pub flavor: Flavor,
17    pub regparm: Option<u32>,
18    pub reg_struct_return: bool,
19}
20
21pub(crate) fn compute_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>, opts: X86Options)
22where
23    Ty: TyAbiInterface<'a, C> + Copy,
24    C: HasDataLayout + HasTargetSpec,
25{
26    if !fn_abi.ret.is_ignore() {
27        if fn_abi.ret.layout.is_aggregate() && fn_abi.ret.layout.is_sized() {
28            // Returning a structure. Most often, this will use
29            // a hidden first argument. On some platforms, though,
30            // small structs are returned as integers.
31            //
32            // Some links:
33            // https://www.angelcode.com/dev/callconv/callconv.html
34            // Clang's ABI handling is in lib/CodeGen/TargetInfo.cpp
35            let t = cx.target_spec();
36            if t.abi_return_struct_as_int || opts.reg_struct_return {
37                // According to Clang, everyone but MSVC returns single-element
38                // float aggregates directly in a floating-point register.
39                if fn_abi.ret.layout.is_single_fp_element(cx) {
40                    match fn_abi.ret.layout.size.bytes() {
41                        4 => fn_abi.ret.cast_to(Reg::f32()),
42                        8 => fn_abi.ret.cast_to(Reg::f64()),
43                        _ => fn_abi.ret.make_indirect(),
44                    }
45                } else {
46                    match fn_abi.ret.layout.size.bytes() {
47                        1 => fn_abi.ret.cast_to(Reg::i8()),
48                        2 => fn_abi.ret.cast_to(Reg::i16()),
49                        4 => fn_abi.ret.cast_to(Reg::i32()),
50                        8 => fn_abi.ret.cast_to(Reg::i64()),
51                        _ => fn_abi.ret.make_indirect(),
52                    }
53                }
54            } else {
55                fn_abi.ret.make_indirect();
56            }
57        } else {
58            fn_abi.ret.extend_integer_width_to(32);
59        }
60    }
61
62    for arg in fn_abi.args.iter_mut() {
63        if arg.is_ignore() || !arg.layout.is_sized() {
64            continue;
65        }
66
67        let t = cx.target_spec();
68        let align_4 = Align::from_bytes(4).unwrap();
69        let align_16 = Align::from_bytes(16).unwrap();
70
71        if arg.layout.is_aggregate() {
72            // We need to compute the alignment of the `byval` argument. The rules can be found in
73            // `X86_32ABIInfo::getTypeStackAlignInBytes` in Clang's `TargetInfo.cpp`. Summarized
74            // here, they are:
75            //
76            // 1. If the natural alignment of the type is <= 4, the alignment is 4.
77            //
78            // 2. Otherwise, on Linux, the alignment of any vector type is the natural alignment.
79            // This doesn't matter here because we only pass aggregates via `byval`, not vectors.
80            //
81            // 3. Otherwise, on Apple platforms, the alignment of anything that contains a vector
82            // type is 16.
83            //
84            // 4. If none of these conditions are true, the alignment is 4.
85
86            fn contains_vector<'a, Ty, C>(cx: &C, layout: TyAndLayout<'a, Ty>) -> bool
87            where
88                Ty: TyAbiInterface<'a, C> + Copy,
89            {
90                match layout.backend_repr {
91                    BackendRepr::Scalar(_) | BackendRepr::ScalarPair(..) => false,
92                    BackendRepr::SimdVector { .. } => true,
93                    BackendRepr::Memory { .. } => {
94                        for i in 0..layout.fields.count() {
95                            if contains_vector(cx, layout.field(cx, i)) {
96                                return true;
97                            }
98                        }
99                        false
100                    }
101                }
102            }
103
104            let byval_align = if arg.layout.align.abi < align_4 {
105                // (1.)
106                align_4
107            } else if t.is_like_darwin && contains_vector(cx, arg.layout) {
108                // (3.)
109                align_16
110            } else {
111                // (4.)
112                align_4
113            };
114
115            arg.pass_by_stack_offset(Some(byval_align));
116        } else {
117            arg.extend_integer_width_to(32);
118        }
119    }
120
121    fill_inregs(cx, fn_abi, opts, false);
122}
123
124pub(crate) fn fill_inregs<'a, Ty, C>(
125    cx: &C,
126    fn_abi: &mut FnAbi<'a, Ty>,
127    opts: X86Options,
128    rust_abi: bool,
129) where
130    Ty: TyAbiInterface<'a, C> + Copy,
131{
132    if opts.flavor != Flavor::FastcallOrVectorcall && opts.regparm.is_none_or(|x| x == 0) {
133        return;
134    }
135    // Mark arguments as InReg like clang does it,
136    // so our fastcall/vectorcall is compatible with C/C++ fastcall/vectorcall.
137
138    // Clang reference: lib/CodeGen/TargetInfo.cpp
139    // See X86_32ABIInfo::shouldPrimitiveUseInReg(), X86_32ABIInfo::updateFreeRegs()
140
141    // IsSoftFloatABI is only set to true on ARM platforms,
142    // which in turn can't be x86?
143
144    // 2 for fastcall/vectorcall, regparm limited by 3 otherwise
145    let mut free_regs = opts.regparm.unwrap_or(2).into();
146
147    // For types generating PassMode::Cast, InRegs will not be set.
148    // Maybe, this is a FIXME
149    let has_casts = fn_abi.args.iter().any(|arg| matches!(arg.mode, PassMode::Cast { .. }));
150    if has_casts && rust_abi {
151        return;
152    }
153
154    for arg in fn_abi.args.iter_mut() {
155        let attrs = match arg.mode {
156            PassMode::Ignore | PassMode::Indirect { attrs: _, meta_attrs: None, on_stack: _ } => {
157                continue;
158            }
159            PassMode::Direct(ref mut attrs) => attrs,
160            PassMode::Pair(..)
161            | PassMode::Indirect { attrs: _, meta_attrs: Some(_), on_stack: _ }
162            | PassMode::Cast { .. } => {
163                unreachable!("x86 shouldn't be passing arguments by {:?}", arg.mode)
164            }
165        };
166
167        // At this point we know this must be a primitive of sorts.
168        let unit = arg.layout.homogeneous_aggregate(cx).unwrap().unit().unwrap();
169        assert_eq!(unit.size, arg.layout.size);
170        if matches!(unit.kind, RegKind::Float | RegKind::Vector) {
171            continue;
172        }
173
174        let size_in_regs = arg.layout.size.bits().div_ceil(32);
175
176        if size_in_regs == 0 {
177            continue;
178        }
179
180        if size_in_regs > free_regs {
181            break;
182        }
183
184        free_regs -= size_in_regs;
185
186        if arg.layout.size.bits() <= 32 && unit.kind == RegKind::Integer {
187            attrs.set(ArgAttribute::InReg);
188        }
189
190        if free_regs == 0 {
191            break;
192        }
193    }
194}
195
196pub(crate) fn compute_rust_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>)
197where
198    Ty: TyAbiInterface<'a, C> + Copy,
199    C: HasDataLayout + HasTargetSpec,
200{
201    // Avoid returning floats in x87 registers on x86 as loading and storing from x87
202    // registers will quiet signalling NaNs. Also avoid using SSE registers since they
203    // are not always available (depending on target features).
204    if !fn_abi.ret.is_ignore() {
205        let has_float = match fn_abi.ret.layout.backend_repr {
206            BackendRepr::Scalar(s) => matches!(s.primitive(), Primitive::Float(_)),
207            BackendRepr::ScalarPair(s1, s2) => {
208                matches!(s1.primitive(), Primitive::Float(_))
209                    || matches!(s2.primitive(), Primitive::Float(_))
210            }
211            _ => false, // anyway not passed via registers on x86
212        };
213        if has_float {
214            if cx.target_spec().rustc_abi == Some(RustcAbi::X86Sse2)
215                && fn_abi.ret.layout.backend_repr.is_scalar()
216                && fn_abi.ret.layout.size.bits() <= 128
217            {
218                // This is a single scalar that fits into an SSE register, and the target uses the
219                // SSE ABI. We prefer this over integer registers as float scalars need to be in SSE
220                // registers for float operations, so that's the best place to pass them around.
221                fn_abi.ret.cast_to(Reg { kind: RegKind::Vector, size: fn_abi.ret.layout.size });
222            } else if fn_abi.ret.layout.size <= Primitive::Pointer(AddressSpace::ZERO).size(cx) {
223                // Same size or smaller than pointer, return in an integer register.
224                fn_abi.ret.cast_to(Reg { kind: RegKind::Integer, size: fn_abi.ret.layout.size });
225            } else {
226                // Larger than a pointer, return indirectly.
227                fn_abi.ret.make_indirect();
228            }
229            return;
230        }
231    }
232}
rustc_target/callconv/x86.rs

rustc_target/callconv/
x86.rs
